Memory Population Guidelines for Intel 4th Gen Xeon Scalable Processors

Intel's 4th Generation Xeon Scalable Processor launched at the beginning of 2023. The most notable change for memory is the introduction of DDR5 with speeds up to 4800MT/s. When designing for memory population, it is vital to take the following into consideration to ensure the best performance and balanced memory access:

• Memory modules must have identical specifications. Each DIMM must have an identical size, speed, and rank.
• Channels are identically populated with either one or two DIMMs.
• Each CPU socket in the server must have an identical memory layout.

Reviewing the 3rd Gen Intel Xeon Scalable Processor Memory Architecture

The Intel 3rd Generation Xeon Scalable Processor introduced four memory controllers and a total of eight memory channels per CPU. Each channel could accept two DIMMs without any degradation of speed. The DIMM sizes seen in server configurations included a range of 8GB - 128GB DIMMs. 

Each of the eight memory channels has a bus speed of 3200MT/s regardless of the number of DIMMs per channel. A two-socket server features up to 32 DIMMs and there are two balanced memory configurations to choose from for maximum performance:

The Intel 4th Gen Xeon Scalable Processor Memory Architecture

The Intel 4th Generation Xeon Scalable Processor continues the four controller and eight channel architecture that was introduced in the previous generation. The memory bus speed has increased to currently support up to 4800MT/s on certain processors. On the processors that support 4800MT/s, it is important to note that the full speed is obtained when only the first DIMM in each memory channel is populated. When the second DIMM in each memory channel is populated, the speed of the memory channel is reduced to 4400MT/s.

Processor models that support a maximum speed of 4400MT/s or 4000MT/s do not have a difference in speed when the second DIMM slots are populated. The new DIMM sizes in server configurations range from 16GB - 256GB DIMMs. The new processors take full advantage of the overall improvements of DD5 including:

• Up to 4800 MT/s Speeds
• Single bit error correction to allow for denser chips
• Lower power usage at 1.1v

A two-socket server features up to 32 DIMMs and there are two balanced memory configurations to choose from for maximum performance:

Intel has added a new XCC die package to the 4th Gen Xeon lineup which adds to the importance of balanced memory configurations. The XCC die divides the processor into four compute tiles. These compute tiles are connected to each other using Intel Embedded Multi-die Interconnect Bridge (EMIB). The four memory controllers are also divided between the compute tiles leaving each compute tile with a dedicated memory controller. When using XCC die processors compared to the monolithic MCC die processors it is crucial to maintain a balanced memory configuration as any unbalanced memory configurations will be required to traverse the EMIB.

Experience 4th Gen Intel Xeon Scalable Processors in the ATC

Intel 4th Generation Xeon Scalable processors utilize workload accelerators and modern architectures to optimize power and performance for current and future use cases.

These processors are available now in DellEMC PowerEdge 16G, HPE ProLiant Gen11, and Cisco UCS M7-series servers. WWT is pleased to demonstrate this technology in our ATC, and we can accommodate virtually any use case or workload.