Solution Overview

With the emergence of the virtual CMTS (vCMTS), it became evident that overall system performance would be determined by the features and processing capabilities of the underlying CPU that resides within it. Intel's 3rd Generation Ice-Lake Xeon Scalable processors have been equipped with newly refined features that offer more efficient processing when dealing with the most compute-intensive workloads within DOCSIS functionality, dataplane packet processing. 

DOCSIS is heavy with encryption and CRC to protect DOCSIS users/customers, but these instructions come at a cost by consuming a significant portion of CPU cycles, causing throughput to become negatively affected. The enhancements made to Ice-Lake's cryptography include dual AES encryption engines per CPU core while offering support for a new type of AVX-512 vector instruction. With the addition of improved cache size, CPU core density, and memory channels, Ice-Lake's added features offer a 35% improvement to single-core processing throughput compared to the previous generation of Xeon processors.  

Ice-Lake packet-processing performance can be demonstrated by v21.10.0 of Intel's vCMTS Reference Dataplane. This Reference Dataplane provides a way to properly characterize peak performance and power consumption of Xeon-based processors in regard to vCMTS dataplane packet processing, and to assist cable service providers in deploying their own vCMTS.

Lab Diagram